Device Structure And Material Exploration For Nanoscale Transistor

There is a compelling need to explore different material options as well as device structures to facilitate smooth transistor scaling for higher speed, higher density and lower power. The enormous potential of nanoelectronics, and nanotechnology in general, offers us the possibility of designing devices with added functionality. However, at the same time, the new materials come with their own challenges that need to be overcome. In this work, we have addressed some of these challenges in the context of quasi-2D Silicon, III-V semiconductor and graphene. Bulk Si is the most widely used semiconductor with an indirect bandgap of about 1.1 eV. However, when Si is thinned down to sub-10nm regime, the quasi-2D nature of the system changes the electronic properties of the material significantly due to the strong geometrical confinement. Using a tight-binding study, we show that in addition to the increase in bandgap due to quantization, it is possible to transform the original in direct bandgap to a direct one. The effective masses at different valleys are also shown to vary uniquely in an anisotropic way. This ultra-thin Si, when used as a channel in a double gate MOSFET structure, creates so called “volume in version” which is extensively investigated in this work. It has been found that the both the quantum confinement as well as the gating effect play a significant role in determining the spatial distribution of the charge, which in turn has an important role in the characteristics of transistor. Compound III-V semiconductors, like Inx Ga1-xAs, provide low effective mass and low density of states. This, when coupled with strong confinement in a nanowire channel transistor, leads to the “Ultimate Quantum Capacitance Limit” (UQCL) regime of operation, where only the lowest subband is occupied. In this regime, the channel capacitance is much smaller than the oxide capacitance and hence dominates in the total gate capacitance. It is found that the gate capacitance change qualitatively in the UQCL regime, allowing multi-peak, non-monotonic capacitance-voltage characteristics. It is also shown that in an ideal condition, UQCL provides improved current saturation, on-off ratio and energy-delay product, but a degraded intrinsic gate delay. UQCL shows better immunity towards series resistance effect due to increased channel resistance, but is more prone to interfacial traps. A careful design can provide a better on-off ratio at a given gate delay in UQCL compared to conventional MOSFET scenario. To achieve the full advantages of both FinFET and HEMT in III-V domain, a hybrid structure, called “HFinFET” is proposed which provides excellent on performance like HEMT with good gate control like FinFET. During on state, the carriers in the channel are provided using a delta-doped layer(like HEMT) from the top of a fin-like non-planar channel, and during off state, the gates along the side of the fin(like FinFET) help to pull-off the carriers from the channel. Using an effective mass based coupled Poisson-Schrodinger simulation, the…