Hardware Implementation of IDP and LINC Methods Using Real Power Amplifiers

Linearization and peak to average power ration reduction are two classical operations when non-linear power amplifiers (PA) are used. If only PA linearization is considered, the high crest factor (PAPR) of the amplified signal causes saturation when input power is higher than the PA saturation power. If only PAPR reduction is implemented alone, PA non-linearities will degrade the signal at low input backoff (IBO). It is necessary to combine the two methods in order to operate the PA with low IBO while having low in band and out of band degradations. Hybrid methods modify both the architecture of the PA for linearization purposes and the PAPR reduction of the amplified signals. In this paper two hybrid methods: Iterative Dichotomy PAPR Reduction (IDP) and Linear amplification using nonlinear components (LINC) are compared in terms of energy efficiency and implementation complexity. Two real PA models with different output saturation powers are used (45dBm and 15dBm) and the power dedicated to the algorithm implementations are quantified using an FPGA implementation. Simulation results shows that the IDP method outperforms the LINC one in terms of energy efficiency.