Design of a Low-dropout Regulator with High Power Supply Rejection Ratio

In this paper,a Low-Dropout Regulator with high power supply rejection ratio and fast response which is implemented in a standard 0.35μm 2P4M CMOS technology is proposed.The proposed LDO circuits achieve high power supply rejection ratio and fast load transient response according to the impedance-attenuated buffer for driving the PMOS pass device.The input voltage varies from 3.3V to 4V,the output voltage is 2.8V,the load current transient varies from 0.5mA to 100mA,the maximum overshoot voltage is less than 1mV during the full load current transient.It reaches-89dB power supply rejection ratio at low flequeucy and about-60dB at 1MHz.