Dielectric pockets – a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15- m PMOS devices showing substantial efficiency in reducing SCE and current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.