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0.13um 32Mb/64Mb embedded DRAM core with high efficient redundancy and enhanced testability
0.13um 32Mb/64Mb embedded DRAM core with high efficient redundancy and enhanced testability
2001
Kikukawa
Tomishima
Tsuji
Kawasaki
Sakamoto
Ishikawa
Abe
Tanizaki
Kato
Uchikoba
Inokuchi
Senoh
Fukushima
Niiro
Maruta
Shibayama
Ooishi
Takahashi
Hidaka
Keywords:
Decoding methods
Dram
Electronic circuit
Embedded system
Testability
core
Redundancy (engineering)
System testing
logic testing
Computer science
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