Gate-Substrate Triggered NMOS (GSTNMOS) with Low Trigger Voltage in the temperature range of 300 K -500 K

In this paper, ESD protection circuits with gate-substrate trigger technique for low trigger voltage and low leakage current in 0.13um CMOS process is proposed. The proposed ESD protection circuit is verified by the transmission line pulse (TLP) system and semiconductor parameter analyzer. The results show that the proposed ESD protection circuit has lower trigger voltage (5.35V) compared with that of conventional GGNMOS protection circuit. And the proposed circuit has lower leakage current (80pA) compared with that of conventional gate substrate triggered NMOS protection circuit. As the temperature increases, breakdown voltage and trigger voltage increases. Also, as temperature increases, holding voltage and second breakdown voltage decrease.