Time synchronization error measuring circuit based on CPLD technology

The utility model provides a time synchronization error measuring circuit based on the CPLD technology. In the circuit, a first input end of an or gate is connected with a reference pulse signal joint point, a second input end of the or gate is connected with a tested pulse signal joint point; a first input end of an AND gate is connected with the tested pulse signal joint point, a second input end of the AND gate is connected with the reference pulse signal joint point; the clock end of a counter is connected with a clock signal joint point, the enabling end of the counter is connected with the output end of the or gate, a zero clearing end of the counter is connected to the output end of the or gate after passing through an inverter; the input end of a second D trigger is connected with the output end of the counter, and the clock end of the second D trigger is connected with the output end of the AND gate. The circuit has the advantages of low efficacy, high measuring accuracy, high integrated level, and simple circuit.