A three-dimensional stacked chip structure and method

A method comprising placing a first plurality of devices over the first die carrier, wherein the plurality of first die and a first carrier devices are combined to form a first composite wafer. A second wafer bonded to the first composite wafer, and bonded by mixing the plurality of first die bonding device to a second device of the plurality of second dies in the wafer. The method further comprising: a first plurality of separating from the first die carrier means, a plurality of first sealing device dies in the sealing material, and forming a first plurality of interconnect structure and the upper sealing device die material. Example embodiments relate to a package and a manufacturing method of the present invention.