Chip package and method of fabricating the same

The invention provides a wafer package and its manufacture method. The chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and extends toward the upper surface to expose the conductive pad. The insulation layer extends from the lower surface and to the upper surface. Portion of the insulation layer is positioned in a throughhole and the insulation layer is formed with a gap to expose the conductive pad. The redistribution layer extends from the lower surface to upper surface, portion of the redistribution layer is positioned in the throughhole and is electrically connected to the conductive pad through the gap. The packaging layer extends from the lower surface to the upper surface, portion of the package layer is positioned in the throughhole. The invention can obviously reduce the cost.