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Acemap > Paper > CMOS 저전압 기준전압발생기를 적용한 향상된 과도응답 특성을 갖는 Capacitor-less LDO 설계

CMOS 저전압 기준전압발생기를 적용한 향상된 과도응답 특성을 갖는 Capacitor-less LDO 설계

2016 
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