A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to achieve both high speed and low power in DRAMs is described. This circuit reduces the excessive operating margin caused by device fluctuations by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve 200-MHz operation in a 1-Gb SDRAM using 0.13-/spl mu/m technology: a cycle-time-progressive control circuit that increases the operating frequency and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. These techniques and circuits reduce the access time to 10 ns, which is 1.2 ns less than that of the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier.