Suppression of NBTI-induced VMIN shifts using hafnium doping to gate poly/SiON interface and optimized NiPt process for 40nm node SRAM cell

Hafnium introduction to poly/SiON interface has been found effective to suppress the increase of minimum operating voltage (V MIN ) caused by NBTI-induced V T shift in 40nm node low power SRAM. In addition, the distribution tail of N+ node junction leakage current has been identified as enhancing VMIN failure due to NBTI, and has been improved by optimizing NiPt silicide process. Finally operation of 32Mbit 0.24µm 2 low power SRAM with VMIN less than 0.9V has been demonstrated.