Analog Versus Digital Control of a Clock Synchronizer for 3 gb/s Data with 3.ov Differential Ecl

quadrant pointer bits are decoded to provide a sign bit; this A novel comparison of analog and digital design techniques is maps the linear integrator output onto the phasor diagram. The a high performmce clock syllchronizatioll scheme. single integrator output is converted into complemeiitary curme digital-controlld synchronizer was fabricated using a rents; the result of this is a non-linear phase characteristic (un0.6pm B~CMOS technology. A new and emitter less it is predistorted) and a non-uniform Signal amplitude from logic gate enabled fully symmetric differential ECL logic oper- the Phase rotator. ations down to 2.5V without forward biasing of the switching The generic systems above can both be made to align a halfcollector-base junctions. The analog solution consumes 1/4 of baud clock to the data if the rotated clock is split into a quadrathe power of the digital. ture pair and if the special phase detector shown in fig. 4 is used. The clock synchronizer It is based on two sampling type detectors [2]. The quadrature clock is used as a marker to differentiate between the positive The clock syiichronizer is a data retiming system using a control aid negative edges of the main clock. The sample of the quadraloop but no oscillator. A reference clock is rotated, by means of ture clock, S, becomes the sign of the sample of the main clock, a phase rotator, to match the phase of the input data. P. The sign bit divides the phasor diagram into two hemispheres. The phase rotator is a circuit that can produce an arbitrary phase After lock, the data from an input which is a quadrature signal pair. Refer to fig. 1. The novel building block for the MUX: latch and XOR gate that The phase selection is in response to a pair of weighting factor make up the phase detector is shown in fig. 5. It is a differential signals (analog) and a pair of quadrant pointer bits (digital). The ECL design that avoids stacking BJTs and hence is capable of core of the rotator is a weighted summer, which interpolates the operation down to 2SV, without forward biasing the switching input phases to produce the output (see for example [l]). The BJTs; this is not possible with conventional ECL where BJTs pointer bits can be used to change the sign of the quadrature must be stacked for some functions. It allows completely symfeed clocks as a method of reaching all quadrants. If the clocks metrical XOR realization, which is required in the phase detecare square wave, bandwidth limiting is required on either the in- tor; see fig. 6. An AND/OR gate is also realizable. The structure put or the output of the rotator. The weighting factor can be gen- is implemented with a metal-progammable cell layout. erated by closed loop control. A phase detector is used to provide a command sigllal to a filter. ne filter output is the weight- Measured silicon results are available for the DCS and simulaillg factor pair. The filter can be digital or analog. tion results are available for the ACS and DCS. Fig.s 7 and 8, show phase and phase-error information for tracking systems. The generic digital-filter clock synchronizer (DCS) is shown in The rotated clock follows the input data phase with a static error fig. 2. The digital filter is made up of a decimator, to ensure loop and some jitter. A comparison of the performance and power stability, and a state machine, whose states form a ring corre- consumption of the two systems is summarized in table 1. spondiiig to the phasor diagram. The states can be decoded to produce the quadrant pointer bits and a digital weighting factor Conclusion