On the avalanche ruggedness of optimized termination structure for 600 V punch-through IGBTs

Abstract In this paper, the current paths in avalanche conditions of a Floating Field Ring (FFR) termination for a Punch-Through (PT) Insulated Gate Bipolar Transistor (IGBT) are analyzed. The design of the termination region is achieved with two different optimization techniques, and both static and dynamic electrical behavior are analyzed by means of 2D TCAD simulations, up to high current density levels. A comprehensive analysis of the Unclamped Inductive Switching (UIS) operation of the proposed terminations is carried-out with electro-thermal simulations. Although the behavior of both structures at low current levels is different, results show the same current crowding effect at the main junction for high current levels, resulting in a reduced conduction area of the overall termination, hence, of the avalanche reliability. Finally, experimental confirmation of filamentary current conduction during UIS test are detected on 600 V commercial devices by means of transient infrared thermography.