A Low Phase Noise Injection-Locked Ring PLL Based a Sub-Sampling Loop

In this paper, an injection-locked phase-locked loop (ILPLL) based a sub-sampling loop (SSL) with low phase noise and low jitter is presented. A sub-sampling loop is used to subsample the ring VCO output with the injection pulse. The SSL is used to detect the phase difference of the output differential pair of the RVCO and generate a control signal to realign the phase of the differential output pair of the RVCO. Therefore, the center of the injection pulse can be made to occur at the zero crossing of the RVCO output by constant adjustment. A 200MHz PLL is developed by use of 55nm CMOS technology. The phase noise is -132 dBc/Hz at 1MHz offsets.