Structure and method of forming an inter-poly dielectric in a field effect transistor with shielded gate

A method of forming a field effect transistor comprising: Forming a trench in a silicon region of a first conductivity type, said trench having a shield electrode, which is opposite to the silicon region is isolated by a shield dielectric; Forming an inter-poly dielectric (IPD) comprising a layer of thermal oxide and a layer of conformal dielectric along an upper surface of the shield electrode; Forming a gate dielectric lining at least the upper grave side walls; and Forming a gate electrode in the trench, wherein the gate electrode is insulated from the shield electrode by the IPD.