A 256-K 13-nanosecond CMOS SRAM

Recently, many types of very high-speed static RAMs (SRAM) using CMOS or BiCMOS technologies have been announced. Even with CMOS SRAMs, which operate in the range of 10 ns access time, both device and circuit technologies and also usage and reliability problems become prominent, and must be solved in order to achieve adequate speed performance. This paper discusses technical problems and their realistic solutions for achieving very-high speed SRAMs using CMOS from the viewpoint of device and circuit technologies. Consequently, short channel MOSFETs using 1.0 μm NMOS and 1.0 μm PMOS gate lengths were used to reduce the access time. In order to reduce the soft-errors that cause problems when high-speed SRAMs are operated with a short cycle time, the Vth of memory cell transistors is set higher than the level in the other circuits. Hence, the soft-error rate is the same when the device is operated with a longer cycle time. With respect to circuit technology, a high sensitivity sense amplifier is used with a smaller gain decrease under low voltage, a circumstance which is suitable to high-speed SRAMs that are sensitive to supply voltage bounce due to electrical noise within the chip. In order to implement systems using high-speed SRAMs, a write-timing control circuit is introduced, which alleviates the timing constraints on the address skew during write timing. Utilizing these technologies with a CMOS process, a 256-K SRAM with an access time of 13 ns has been achieved.