Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration

The apparent saturation of aggressive Moore’s law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( $\leq 50~\mu \text{m}$ ) using fine-pitch ( $\leq 10~\mu \text{m}$ ) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal–metal [copper–copper (Cu–Cu)] thermal compression bonding was developed. Using this process, sub-10- $\mu \text{m}$ -pitch interconnects with a low specific contact resistance of $\leq 0.7~\Omega \cdot \mu \text{m}~^{\mathrm{ 2}}$ and high shear force of 90 N for 4-mm 2 dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( $\leq 500~\mu \text{m}$ ) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency ( $23\times $ higher data bandwidth, 3– $65\times $ lower latency, and 5– $40\times $ lower energy per bit compared to existing integration schemes.