Prediction of Power Supply Noise From Switching Activity in an FPGA

Switching current drawn by an integrated circuit (IC) creates dynamic power supply noise on the IC and on the printed circuit board (PCB), which in turn causes jitter in $I$ / $O$ signals and reduces the maximum clock frequency. Predicting power supply noise is challenging due to the complexity of determining the dynamic current drawn by the IC and the impedance of the power delivery network. In this paper, a methodology is developed for predicting dynamic power supply noise on the PCB resulting from logic activity in a field-programmable gate array (FPGA). Time-domain switching currents within the FPGA are found by performing power simulations of the implemented logic over small time intervals. A high-frequency model of the die–package–PCB power delivery network is developed based on the inductance and capacitance of the package and die and a cavity model description of the PCB. The technique is shown to accurately predict noise on the PCB in both the time and frequency domains.