Characterization Scheme for Plasma-Induced Defect Creation due to Stochastic Lateral Straggling in Si Substrates for Ultra-low Leakage Devices

Precise control of low-density defect creation during plasma processing is critical for designing ultra-low leakage devices. Unlike conventional vertical defect creation mechanisms, the "stochastic lateral straggling" of incident particles during plasma processing is accepted as inevitable. Herein, a new characterization scheme is demonstrated to assess the density and profile of defects in the lateral direction and to verify their impact using CMOS image sensor-based structures. The junction leakage current (dark current) significantly depended on the lateral distance after plasma exposure, indicating that the test structures could quantitatively assess the defect creation in the lateral direction. A 3D (vertical and lateral) defect map is presented, which is indispensable for the performance design of ultra-low leakage devices such as CMOS image sensors.