Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

The increased complexity of CMOS transistor processing has led to limited scaling of high density SRAM cell at advanced technology nodes. STT-MRAM appears to be a promising candidate for replacing last level caches (LLC). This paper addresses design technology co-optimization (DTCO) of STT-MRAM technology and analyzes its viability as a LLC (compared to SRAM) for the high performance computing (HPC) domain (while maintaining a constraint of occupying merely 43.3% of SRAM macro area at identical capacities). This is the first study that breaks down a power, performance and area (PPA) comparison between SRAM and STT-MRAM based LLCs at the 5nm node. The STT-MRAM design and analysis is based on a silicon verified compact model and can be realized using 193i single patterning at the 5nm node. Our STT-MRAM design manages to achieve a nominal access latency <2.5ns and <7.1ns for read and write operations respectively. We also observe a clear and significant trend of increasing energy gains with respect to SRAM for increasing LLC sizes with the crossover points for STT-MRAM read and write operations at 0.4MB and 5MB respectively.