Area Optimization of FIR Filter and its Implementation on FPGA

Digital Signal Processing is omnipresent in the modern world. Filtering is most important operation of Digital Signal Processing. FIR digital filters are widely used in DSP by the virtue of its stability, linear phase, fewer finite precision error and efficient implementation. First Low pass FIR Filter is designed by choosing CSD algorithms and MATLAB FDA Tool is used Coefficients calculation. The CSD numbers has the minimum number of non-zero digits and no consecutive nonzero digits. Now the multipliers in the digital filters are realized with shifters, adders and subtractors. The use of CSD expression can reduce the number of adders and subtractors. To multiply with CSD number only shift and add operations are required. In this paper multiplication with CSD and binary number is simulated and implemented on the Spartan device, the results shows that the area in the terms of number of slices optimized by 80% in CSD algorithm. Index Terms—CSD, FIR filter, FPGA