A simplified distribution parasitic capacitance model for on-chip spiral inductors
2006
A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.
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