Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm

The explosive growth in VLSI Design technology has been juxtaposed with the complexities, hence requiring a more efficient and faster way of miniaturization, with little to none human efforts. The way to go is to explore novel methodologies to find out the best as well as the least Time-Consuming method to find the optimum solution without compromising with quality. Here this paper describes the use of the genetic algorithm to find the most optimum path in a smaller number of iterations by the judicial use of controlled mutation at various stages, all the more so with the least impact on the optimization result with a robust structure. Hence enabling large VLSI circuits to be miniaturized with least cross over, by which circuit efficiency, as well as Cost-Saving, can be achieved in the least time possible with high accuracy at the expense of a very least possible trade-off between time and cost.