Reliability enhanced data processing system capable of runtime fault recovery

In order to enhance the reliability of Big Data transmission and real-time processing in radiation environment, a reliability enhanced FPGA system with runtime fault recovery is presented in this work. This technique is proposed based on selective module redundancy and dynamic partial reconfiguration in order to improve the performance and reliability of systems implemented on SRAM-based FPGAs with fault tolerance and runtime recovery. Coarse-grained TMR architecture and fine-grained TMR architecture combining with dynamic reconfiguration are used to protect the system against soft errors caused by SEU. Fault detection units based on majority voter and XNOR gate are inserted in each redundancy module, and the built in-slice carry-chains are used to merge the large number of error flags produced by the fault detection units. The results show that the improvements in recovery time and reliability are achieved by the proposed technique.