An Automated Tool for Implementing Deep Neural Networks on FPGA

FPGA based Deep Neural Networks provide the advantage of high performance, highly parallel implementation with very low energy requirements. A designer must consider various configuration choices, processing components, data-flow types, local memory hierarchy, and fixed-data-precision for a DNN implementation. An exploration tool is essential for building a reconfigurable, fast, and efficient DNN hardware accelerator. We present a methodology to automatically create an optimized FPGA-based hardware accelerator given DNNs from standard machine learning frameworks. We generate a High-Level-Synthesis (HLS) code depending on the user preferences with a set of optimization pragmas. For a faster and cost-effective hardware accelerator, the tool employs a software-model to estimate the execution time and hardware utilization using trained machine-learning models. The model evaluation results show that our framework performance speed-up compares well with the state-of-the-art accelerators using Xilinx FPGA platforms.