Identifying the Location of Hole-Induced Gate Degradation in $\text{LPCVD} -\text{SiN}_{x}/\text{GaN}$ MIS-FETs under High Reverse-Bias Stress

When $\mathbf{SiN}_{\boldsymbol{x}}/\mathbf{GaN}$ MIS-FETs are under high reverse-bias stress, holes can be generated by impact ionization, leak to gate electrode through the gate dielectric and generate defects that induce $\boldsymbol{V}_{\mathbf{TH}}$ instability. In this work, we identify the location of such degradation by separately probing $\boldsymbol{V}_{\mathbf{TH}}$ at source-side and drain-side of the MIS channel. It is revealed that the hole-induced gate degradation under the reverse-bias stress is more uniformly distributed along the gate with a less negative $\boldsymbol{V}_{\mathbf{GS}}$ . As a result, the stability of device under high reverse-bias stress is enhanced. To further suppress the degradation, holes should be prevented from either going through or accumulating under the gate dielectric.