A novel layout automation flow to facilitate test chip design for standard cell characterization

Variation in transistor characteristics increases greatly as feature sizes scaling down, which poses a challenge to the model credibility of transistors used in standard cells. A test array consisting of addressable characterization vehicle and specific transistor test structures extracted from standard cells with product-alike environment is utilized for circuit performance and variability characterization, and is called standard cell based addressable test chip (SCB-ATC). In this paper, we describe an automated flow to facilitate SCB-ATC layout design in FinFET technology. The specific transistor test structures can be generated in a design rule error-free manner by virtue of keeping FEOL and MEOL unchanged and BEOL slightly modified. After applying the proposed design flow to a 16nm FinFET standard cell library, a 32×64 array size test chip has been created within 3 days and manufactured for silicon testing, the results further confirm the feasibility and effectiveness of this procedure.