A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance

A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm 2 in 40nm CMOS.