Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits

The complexity of Random Telegraph Noise (RTN) under digital circuit operations makes it difficult to predict its impacts without accurate modeling and simulation. However, properly integrating RTN into circuit simulation is challenging due to its stochastic nature. In this paper, RTN is comprehensively modeled and embedded into BSIM. A circuit simulation methodology based on industry-standard EDA tools is proposed, resolving the stochastic property, the AC effects, and the coupling of RTN and circuits that are crucial for accurate predictions of impacts of RTN. Using the compact model and proposed method, impacts of RTN on RO and SRAM are demonstrated, which ascertains their applicability to different type of circuits.