Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics

We propose an extraction method of process variation utilizing D-Flip-Flop (DFF) data retention characteristics and Ring Oscillator(RO) oscillation delay. Extracted process variation is modeled as PMOS and NMOS threshold voltage variations. Retention characteristics of the DFF circuit has different sensitivity to threshold voltage variation from the RO circuit. A DFF circuit is newly introduced as a complementary test structure of the conventional RO circuit for process variation extraction. By combining the RO circuit and the DFF circuits, we can accurately estimate the shift of global process variation. The test structure is implemented into silicon chip and the amount of global variation shift is extracted from measured data.