Impact of the Angle of Incidence on Negative Muon-induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs

Muon-induced single event upset (SEU) is predicted to increase with technology scaling. Although previous works investigated the dependencies of muon-induced SEU cross sections on energy, voltage, and technology, the angle of incidence of terrestrial muons is not always perpendicular to the chip surface. Consequently, the impact of the angle of incidence of muons on SEUs should be evaluated. This study conducts negative muon irradiation tests on bulk and fully depleted silicon on insulator static random access memories at two angles of incidence: 0° (vertical) and 45° (tilted). The tilted incidence drifts the muon energy peak to a higher energy as expected. However, the SEU characteristics in the bulk device between the vertical and tilted incidences, including the voltage dependences of the SEU cross sections and multiple cells upset patterns, are similar despite the unexpected impact on the SEU cross section at an operating voltage of 0.4 V.