Exploiting Rising and Charge-Sharing Voltage for Power Management in High Speed Domino Circuits

In this paper a Low power V dd Management (LPM) mechanism is proposed to design power performance manageable high speed dynamic circuits the objective of the proposed low power manageable design is to maintain high performance while decreasing the power consumption of the Domino Circuits. A test chip has been successfully validated to achieve 65% dynamic power consumption 13% static power consumption respectively using TSMC 0.13µm CMOS Technology.