Robust and low power register file in 65 nm technology

A register file (RF) with 32 × 32 capacity and 4-read 2-write (4R2W) ports is presented and analyzed in detail. A new output structure using a MUX and a latch is proposed. It eliminates any dynamic or analog circuit in the read path, and thus it can improve robustness and reduce power at the same time. We also simplify the timing sequence due to the output scheme. The simplified timing circuit not only cuts down the power but also improves the robustness. In addition, less power is achieved when successive read of “0 or “1 is performed. The RF has been fabricated in TSMC 65 nm technology, and the chip test demonstrates that it can operate at 0.8 GHz, consuming 7.2 mW at 1.2 V.