Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

The conventional design techniques struggle with integration density and constantly strengthening requirements of today's nanometer technology. Timing-critical paths analysis is one of such tasks. It has applications in critical path identification, path delay fault simulation, circuit reliability analysis e.g. Bias Temperature Instability (BTI) induced aging, and in several others. In this paper, we propose a scalable simulation based hierarchical technique for explicit identification of true timing-critical paths in sequential circuits. We explore the circuits at two levels - at the flat gate-level and at a higher level as a network of modules or sub-circuits. The result of timing analysis carried out at the gate-level is used for calculating the delays on the topological critical paths through the network of higher level modules. To speed-up the module level timing analysis, the theory of Structurally Synthesized BDDs (SSBDD) is used. Experimental results demonstrate considerable speed-up of the SSBDD based timing analysis, compared to the flat gate-level analysis.