EUV OPC modeling and correction requirements

In this paper we discuss the EUV OPC modeling challenges and potential solutions, as well as OPC integration requirements to support the forthcoming application of EUV lithography. 10-nm-node OPC modeling is considered as an example. Wafer and mask process data were collected for calibration and verification patterns, to understand the mask making error/OPC model interactions. Several factors, including compact mask topography modeling impact, were analyzed by means of rigorous simulations and model fitting. This was performed on a large-scale data set, to ensure accurate characterization of the OPC modeling strategies, using a large number of patterns.