Method to test redundant stuck-at faults considering logic gates' delay

This paper proposes a method to test redundant stuck-at faults of digital circuits by I DDT testing.The scheme uses two patterns and considers the path delay of logic gates.In order to test two kinds of redundant stuck-at faults,the algorithms which can activate and transmit the faults are presented.SPICE simulation experimental results show the proposed method can distinguish the fault circuits and the fault free circuits effectively,and it can be used as a beneficial supplement of voltage test method.