GDI failure mechanism investigation and improvement in HK process

Scaling down the complementary metal oxide semiconductor field effect transistors (COMS FET) requires involvement of High K (HK) metal gate technology in sub 45nm nodes. HK enables significant lower leakage at similar effective oxide thickness (EOT) to SiO 2 by effective suppression of direct tunneling. However, stress induced leakage current (SILC) and defects in the ultrathin interlayer in HK stack have been causing severe reliability concerns. In this work, we analyzed the gate dielectric integrity (GDI) performance in 28nm High K metal gate (HKMG) process with Vramp test and discussed the root cause of SILC and Vramp failure. Based on our experiments, we proposed an optimized process, which employs post deposition anneals (PDA) and decoupled plasma nitridation (DPN) process to passivate bulk trap in bulk HK to improve SILC. In-situ steam generation (ISSG) oxide and physical vapor deposition (PVD) TiN work function layer are also main contributors to improve GDI performance.