High Performance Full Chip Device Profiling and DOE selection for Physical and Parametric Yield Monitoring

Products today can contain tens of billions of devices with hundreds of millions of unique layout contexts. The electrical performance of these transistors (e.g. Idsat, Vth, etc.) are highly sensitive to Layout Dependent Effects (LDE). This paper describes a novel and high-performance flow to identify a representative sampling of devices for LDE parameter extraction and simulation. Common and outlier devices can be chosen for process control monitoring. This can reduce the gap between models and silicon.