AC-Boosting Frequency Compensation with Double Pole-Zero Cancellation for Multistage Amplifiers

In this paper, we present an AC-boosting compensation topology with double pole-zero cancellation (ACBC-DPZ) for a multistage amplifier driving a very large capacitive load. The proposed technique modifies the original AC-boosting compensation (ACBC) topology to increase the power-bandwidth efficiency and reduce the size for the output power transistor and compensation capacitor. Simulation results show that the ACBC-DPZ amplifier using a CSM 0.18 μm CMOS process can achieve a unity gain bandwidth of 14 MHz and an average slew rate of 3.88 V/μs at 1500 pF load. The amplifier dissipates 2.55 mW at a 1.8 V supply.