Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays

Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology for last-level embedded caches. It exhibits ultra-high density (3–4X of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS. As the design and fabrication process mature for the STT-MRAM, there is a need to study the various fault models that can affect this novel memory technology. This work presents a comprehensive analysis of fault models which represent both parametric variations as well as defects (opens and shorts) in STT MRAM. Sensitivity of Read, Write and Retention to process (material and lithographic) parameters, defects (both intra-cell and inter-cell) and data patterns are studied.