Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers

This paper presents the a design methodology for 112Gb/s PAM4 ADC-based receivers. The methodology is based on channel equalization to validate the specifications is proposed. A complete high-speed serial link in MATLAB Simulink was simulated. It is demonstrated the receiver is capable to equalize input data with channel losses close and up to 30dB at Nyquist Frequency. A combination of CTLE, long FFE taps with one-tap DFE presents as the best solution to cancel ISI. The resulting Bit Error Rate (BER) is within the specified range of 1×10–4 to 1×10-5.