Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI

This paper presents a device-level analysis of a BiPMOS pull-down structure for low-voltage dynamic BiCMOS logic gate circuit suitable for VLSI using sub-quarter-micron BiCMOS technology. Thanks to the BiPMOS pull-down structure, despite the slow turn-off of the bipolar device, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one. >