19.3 A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors

Conventional processors regulate the supply voltage (V DD ) and clock frequency (F CLK ) in two separate and independent control loops. A buck converter, switched-capacitor, or low-dropout (LDO) voltage regulator are example control loops for regulating V DD based on a reference voltage (V REF ). Processors commonly integrate a phase-locked loop (PLL) to separately regulate F CLK based on a reference clock frequency (F REF ), where the F CLK control loop is unaware of the impact of dynamic parameter variations such as V DD droops or temperature changes on the path-timing margin because the PLL voltage-controlled oscillator (VCO) operates on a separate analog voltage. For this reason, conventional processors require either V DD or F CLK guardbands or adaptive and resilient circuits to ensure correct functionality while in the presence of worstcase dynamic parameter variations [1].