Carrierless thin wafer handling for 3D integration

Three-dimensional (3D) integration wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSV). This technology offers great potential improvement over the traditional 2D planar integrated circuits by many ways. A key issue in 3D integration is fabricating ultrathin wafer with TSV. This paper presents a method to fabricate ultrathin wafer by a locally selective thinning technique. Deep reactive ion etching (DRIE) has been utilized to thin the wafer and to prepare the high aspect ratio vias, which are filled with copper by using bottom-up electroplating technique. This method simplifies the fabricating process of ultrathin wafer, comparing to the conventional technology, which grinds the whole wafer with temporary supporting substrate. The surface of thinned wafer has been examined by shadow moire co-planarity measuring system and the result is acceptable for following bonding process. The experimental results verify the feasibility of proposed method.