Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime

Ultra-low power digital circuit design using sub-threshold supply voltages has recently been popularized for energy-constrained systems, sensor networks and bio-sensor applications. The conventional method to improve digital circuit operation in the sub-threshold region is to design every logic cell manually, requiring complete re-design and re-characterization for every process node. This proposed work introduces a computational design automation that tests every cell in a standard cell library for proper operation in the sub-threshold region, eliminating cells that perform poorly. The result of this culling process is improved sub-/near-threshold operation for any standard cell library, improving delay, area, and energy. Monte-Carlo simulation results of a synthesized 90nm-CMOS Floating-Point Adder verifies improved mean timing delay (32%) and overall energy per computation (37%) of the culled standard cell library design over a regular synthesized design.