16:1 retiming multiplexer for 10 Gbit/s in Si production technology

A 16:1 multiplexer was realised for a 10 Gbit/s data transmission system. Only a single 10 GHz clock is used to generate all internal select and clock signals. No external delay lines are needed to achieve a proper clock signal for output retiming. The data jitter is /spl sim/3 ps under worst case operating conditions.