Implementation of Advanced Encryption Standard (AES) 192 Bit on FPGA

This paper presents an efficient hardware implementation of the Advanced Encryption Standard (AES) 192 bit Encryption in which we have used High Level Language (HLL) tool ISE Design Suite 14.4 Tool (Xilinx System Generator).In this work, System Generator approach on FPGA platforms has been used because it directly maps the design. The System Generator approach is best for Encryption. Our approach is better in terms of performance. Our proposed FPGA platform for the implementation of this work is Virtex-5vlx50t (ff1136) FPGA kit from Xilinx. We have used conventional blocks of Xilinx System Generator to get optimum performance in terms of speed. It operates on 100.251 MHz with throughput of 1.069 Gbps.