The Total Release Method for FIB In-Situ TEM Sample Preparation

In 1965, Gordon Moore forecast that the microprocessor industry would continually scale to smaller feature sizes and the number of transistors would double every 18 months. Scaling below the 100nm node, combined with the implementation of copper and low dielectric constant insulators to increase the processor speed, has produced the situation in which SEM inspection no longer offers suitable resolution to image key artifacts and structures. The transmission electron microscope (TEM), once considered more of a development tool, is now in the forefront for process control and failure analysis, especially for measurements such as the thickness of semiconductor device non-planar barrier and seed layers