Degradation Mechanism for Continuous-Wave Green Laser-Crystallized Polycrystalline Silicon n-Channel Thin-Film Transistors under Low Vertical-Field Hot-Carrier Stress with Different Laser Annealing Powers

For a thin-film transistor (TFT) in a display, the hot-carrier (HC) effect still plays an important role in causing the degradation of source/drain (S/D) current and reflects the problem of reliability. In this study, the proposed TFT devices were treated by continuous-wave green laser annealing on their Si-channels and also activated by the thermal-furnace method. Furthermore, using the shifts of capacitance–voltage (C–V) curves and observing the curve variation before and after stress, the targeted number of interface states and bulk traps in a channel can be realized. Indirectly, the degradation level of the tested device can be quantified when the stressed drain voltage is indicated in the horizontal direction, the gate voltage is slightly larger than the threshold voltage and is labeled in the vertical direction, and both are applied. The critical mechanism in degradation involves the location and number of interface states and grain boundary traps. These traps are mainly attributed to the interface states between SiO2 and channel polycrystalline silicon, the grain boundary traps, and the grain traps.